In a system on chip (SOC) application, the system dynamically powers down unused sections and powers up those sections when they are accessed. In some circuit designs, when a section is not active, such as when the section is powered down, headers and/or footers are deactivated or turned off to cut off the leakage paths from a power supply, including a high voltage power supply VDD or a low voltage power supply VSS. Further, the headers and footers are activated to enable normal operation of a section when the section is activated from an inactive state in a wake-up process.
In some circuit designs, a power domain including headers or footers is separated from another power domain. To wake up different power domains in a chip, in some approaches, individual power domains are sequentially powered on in a daisy chain manner. The daisy chain mechanism causes a relatively complex circuit design and more area penalty.
Like reference symbols in the various drawings indicate like elements.